library ieee;
use ieee.std_logic_1164.all;

entity aludec is
    port(
    AluOp: in std_logic_vector(1 downto 0);
    Funct: in std_logic_vector(5 downto 0);
    AluControl: out std_logic_vector(2 downto 0)
    );
end aludec;

architecture behav of aludec is
begin
    AluControl <=
        "010"
            when AluOp = "00" else
        "110"
            when AluOp = "01" else
        "010"
            when AluOp(1) = '1' and Funct = "100000" else
        "110"
            when AluOp(1) = '1' and Funct = "100010" else
        "000"
            when AluOp(1) = '1' and Funct = "100100" else
        "001"
            when AluOp(1) = '1' and Funct = "100101" else
        "111"
            when AluOp(1) = '1' and Funct = "101010" else
        (others => '-');
end behav;
